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1 ? fn9098.3 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. dynamic vid? is a trademark of intersil americas inc. copyri ght ? intersil americas inc. 2002-2004. all rights reserved. all other trademarks mentioned are the property of their respective owners. ISL6561 multi-phase pwm controller with precision r ds(on) or dcr differential current sensing for vr10.x application the ISL6561 controls microprocessor core voltage regulation by driving up to 4 synchron ous-rectified buck channels in parallel. multi-phase buck converter architecture uses interleaved timing to multiply channel ripple frequency and reduce input and output ripple currents. lower ripple results in fewer components, lower component cost, reduced power dissipation, and smaller implementation area. microprocessor loads can gen erate load transients with extremely fast edge rates. the ISL6561 features a high bandwidth control loop and ripple frequencies of >4mhz to provide optimal response to the transients. today?s microprocessors requir e a tightly regulated output voltage position versus load current (droop). the ISL6561 senses current by utilizing pat ented techniques to measure the voltage across the on resistance, r ds(on) , of the lower mosfets or dcr of the output inductor during the lower mosfet conduction intervals. current sensing provides the needed signals for precision droop, channel-current balancing, and over-current protection. the accuracy of the current-se nsing method is enhanced by the ISL6561?s temperature co mpensation function. droop accuracy can be affected by increasing r ds(on) or dcr with elevated temperature. th e ISL6561 uses an internal temperature-sensing element to provide programmable temperature compensation. co rrectly applied, temperature compensation can completely nullify the effect of r ds(on) or dcr temperature sensitivity. a unity gain, differential amplifier is provided for remote voltage sensing. any potential difference between remote and local grounds can be completely eliminated using the remote-sense amplifier. eliminating ground differences improves regulation and protec tion accuracy. the threshold- sensitive enable input is available to accurately coordinate the start up of the ISL6561 wit h any other voltage rail. dynamic-vid? technology allows seamless on-the-fly vid changes. the offset pin allows accurate voltage offset settings that are independent of vid setting. the ISL6561 uses 5v bias and has a built-in shunt regulator to allow 12v bias using only a small external limiting resistor. features ? precision multi-phase core voltage regulation - differential remote voltage sensing - 0.5% system accuracy over life, load, line and temperature - adjustable reference-voltage offset ? precision r ds(on) or dcr current sensing - integrated programmable temperature compensation - accurate load-line programming - accurate channel-current balancing - differential current sense - low-cost, lossless current sensing ? internal shunt regulator for 5v or 12v biasing ? microprocessor volta ge identification input - dynamic vid? technology - 6-bit vid input - 0.8375v to 1.600v in 12.5mv steps ? threshold-sensitive enable function for synchronizing with driver por ? over current protection ? over-voltage protection - no additional external components needed - ovp pin to drive opitional crowbar device ? 2, 3, or 4 phase operation ? greater than 1mhz o peration (> 4mhz ripple) ? pb-free available ? qfn package option - qfn compliant to jedec pub95 mo-220 qfn - quad flat no leads - product outline - qfn near chip scale package footprint; improves pcb efficiency, th inner in profile ordering information part number temp. (c) package pkg. dwg # ISL6561cr 0 to 70 40 ld 6x6 qfn l40.6x6 ISL6561crz (note) 0 to 70 40 ld 6x6 qfn (pb-free) l40.6x6 ISL6561ir -40 to 85 40 ld 6x6 qfn l40.6x6 ISL6561irz (note) -40 to 85 40 ld 6x6 qfn (pb-free) l40.6x6 add ?-t? suffix for tape and reel. note: intersil pb-free products em ploy special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. data sheet june 2004
2 ISL6561 pinout ISL6561 (40-pin qfn) top view vid3 vid2 vid1 vid0 vid12.5 ofs dac gnd gnd pgood ovp gnd fs gnd enll en tcomp vid4 ref vcc pwm4 isen4+ isen4- isen2- isen2+ pwm2 pwm1 isen1+ isen1- isen3- isen3+ vsen rgnd vdiff comp gnd fb idroop gnd pwm3 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20
3 ISL6561cr block diagram i_trip ovp latch channel power-on reset (por) pwm1 pwm2 pwm3 pwm4 gnd vcc fb fs s clock and vid4 vid3 vid2 vid1 comp vsen generator sawtooth isen3- isen4+ vid0 rgnd vdiff pgood ovp en 1.24v i_tot dynamic vid d/a sample hold & current balance channel detect ofs three-state isen1+ isen2- channel current sense ovp vid12.5 soft start and fault logic offset ref +200mv r x1 e/a oc pwm pwm pwm pwm q tcomp t enll dac isen4- isen3+ isen2+ isen1- idroop ISL6561
4 ISL6561 typical application - 4-phase buck converter with rds,on sensing and external ntc vid3 +5v pwm vcc boot ugate phase lgate gnd +12v vin pwm vcc boot ugate phase lgate pvcc gnd +12v vin pwm vcc boot ugate phase lgate pvcc gnd +12v hip6601b driver vin pwm vcc boot ugate phase lgate pvcc gnd +12v hip6601b driver vin vid4 pgood vid2 vid1 vid0 vsen vdiff fb comp vcc gnd rgnd en isen1+ pwm1 pwm2 isen2+ pwm3 isen3+ pwm4 isen4+ ISL6561 p load vid12.5 isen1- isen2- isen3- isen4- tcomp ref dac ovp ntc thermistor fs ofs hip6601b pvcc enll vidpgood idroop hip6601b driver driver +12v r t
5 typical application - 4-ph ase buck converter with r ds(on) sensing and internal ptc vid3 +5v pwm vcc boot ugate phase lgate gnd +12v driver vin pwm vcc boot ugate phase lgate pvcc gnd +12v vin pwm vcc boot ugate phase lgate pvcc gnd +12v hip6601b driver vin pwm vcc boot ugate phase lgate pvcc gnd +12v hip6601b driver vin vid4 pgood vid2 vid1 vid0 vsen vdiff fb comp vcc gnd rgnd en isen1+ pwm1 pwm2 isen2+ pwm3 isen3+ pwm4 isen4+ ISL6561 p load vid12.5 isen1- isen2- isen3- isen4- tcomp ref dac ovp fs ofs driver hip6601b pvcc enll vidpgood idroop hip6601b +12v r t ISL6561
6 typical application - 4-phase buck converter with dcr sensing and external ntc vid3 +5v pwm vcc boot ugate phase lgate gnd +12v vin pwm vcc boot ugate phase lgate pvcc gnd +12v vin pwm vcc boot ugate phase lgate pvcc gnd +12v hip6601b driver vin pwm vcc boot ugate phase lgate pvcc gnd +12v hip6601b driver vin vid4 pgood vid2 vid1 vid0 vsen vdiff fb comp vcc gnd rgnd en isen1+ pwm1 pwm2 isen2+ pwm3 isen3+ pwm4 isen4+ ISL6561 p load vid12.5 isen1- isen2- isen3- isen4- tcomp ref dac ovp ntc thermistor fs ofs driver hip6601b pvcc enll vidpgood idroop hip6601b driver +12v r t ISL6561
7 ISL6561 typical application - 4-phase buck conver ter with dcr sensing and internal ptc vid3 +5v pwm vcc boot ugate phase lgate gnd +12v driver vin pwm vcc boot ugate phase lgate pvcc gnd +12v vin pwm vcc boot ugate phase lgate pvcc gnd +12v hip6601b driver vin pwm vcc boot ugate phase lgate pvcc gnd +12v hip6601b driver vin vid4 pgood vid2 vid1 vid0 vsen vdiff fb comp vcc gnd rgnd en isen1+ pwm1 pwm2 isen2+ pwm3 isen3+ pwm4 isen4+ ISL6561 p load vid12.5 isen1- isen2- isen3- isen4- tcomp ref dac ovp fs ofs driver hip6601b pvcc enll vidpgood idroop hip6601b +12v r t
8 absolute maximum ratings supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7v input, output, or i/o voltage (except ovp)gnd -0.3v to v cc + 0.3v ovp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15v sd (human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4kv esd (machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300v esd (charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . >2kv operating conditions supply voltage, vcc (5v bias mode, note 3) . . . . . . . . . . +5v 5% junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to 125c thermal information thermal resistance ja ( c /w) jc ( c /w) qfn package (notes 1, 2) . . . . . . . . 32 3.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (soic - lead tips only) caution: stress above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress onl y rating and operation of the device at these or any other conditions above those indicated in th e operational section of this specification is not implied. notes: 1. ja is measured in free air with the component mounted on a high e ffective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside . electrical specifications operating conditions: vcc = 5v or icc < 25ma (note 3), t j = 0 c to 105 c . unless otherwise specified parameter test conditions min typ max units vcc supply current nominal supply vcc = 5vdc; en = 5vdc; r t = 100 k ?, isen1 = isen2 = isen3 = isen4 = -70 a -1418ma shutdown supply vcc = 5vdc; en = 0vdc; r t = 100 k ? -1014ma shunt regulator vcc voltage vcc tied to 12vdc thru 300 ? resistor, , r t = 100k ? 5.6 5.9 6.2 v vcc sink current vcc tied to 12vdc thru 300 ? resistor, r t = 100k ? --25ma power-on reset and enable por threshold vcc rising 4.2 4.31 4.50 v vcc falling 3.7 3.82 4.00 v enable threshold en rising 1.22 1.24 1.26 v hysteresis 100 mv fault reset 1.10 1.14 1.18 v enll input logic low level --0.4v enll input logic high level 0.8 - - v enll leakage current enll=5v 1 a reference voltage and dac system accuracy (vid = 1.2v-1.6v, t j = 0 c to 85 c ) (note 4) -0.5 - 0.5 %vid system accuracy (vid = 0.8375v-1.1875v t j = 25 c ) (note 4) -0.5 - 0.5 %vid system accuracy (vid = 0.8375v- 1.1875v, t j = 0 c to 85 c ) (note 4) -0.6 - 0.6 %vid vid pull up -65 -50 -35 a vid input low level --0.4v vid input high level 0.8 - - v dac source/sink current vid = 010100 -200 - 200 a ref source/sink current -50 - 50 a pin-adjustable offset voltage at ofs pin offset resistor connected to ground 485 500 515 mv vcc = 5.00v, offset resistor connected to vcc 2.91 3.00 3.09 v ISL6561
9 oscillator accuracy r t = 100 k ? -10 - 10 % adjustment range 0.08 - 1.5 mhz sawtooth amplitude -1.5- v max duty cycle - 66.7 - % error amplifier open-loop gain r l = 10k ? to ground - 80 - db open-loop bandwidth c l = 100pf, r l = 10k ? to ground - 18 - mhz slew rate c l = 100pf 4.5 6.0 7.5 v/ s maximum output voltage 4.0 4.3 - v output high voltage @ 2ma 3.7 - - v output low voltage @ 2ma - - 1.35 v remote-sense amplifier bandwidth -20-mhz output high current vsen - rgnd = 2.5v -500 - 500 a output high current vsen - rgnd = 0.6 -500 - 500 a pwm output pwm output voltage low threshold iload = 500 a --0.3v pwm output voltage high threshold iload = 500 a 4.3 - - v temperature compensation temperature compensation current @ 40 c and tcomp = 0.5v 10 15 20 a temperature compensation transconductance -1-1 a/v/ c sense current sensed current tolerance isen1 = isen2 = isen3 = isen4 = 80 a 74 81 91 a over-current trip level 98 110 122 a power good and protection monitors pgood low voltage i pgood = 4ma - - 0.4 v under-voltage offset from vid vsen falling 72 74 76 %vid over-voltage threshold voltage above vid, after soft start (note 5) 180 200 220 mv before enable 1.63 v vcc < por threshold 1.7 1.8 1.87 v over-voltage reset voltage vcc por threshold, vsen falling - 0.6 - v vcc < por threshold - 1.5 - v ovp drive voltage i ovp = -100ma, vcc = 5v - 1.9 - v minimum vcc for ovp 1.4 - - v notes: 3. when using the internal shunt regulator , vcc is clamped to 6.02v (max). current must be limited to 25ma or less. 4. these parts are designed and adjusted for accuracy with all errors in the voltage loop included. 5. during soft start, vdac rises from 0 to vid. the over-v oltage trip level is the higher of 1.7v and vdac + 0.2v. electrical specifications operating conditions: vcc = 5v or icc < 25ma (note 3), t j = 0 c to 105 c . unless otherwise specified parameter test conditions min typ max units ISL6561
10 functional pin description vcc - supplies all the power necessary to operate the chip. the controller starts to operate when the voltage on this pin exceeds the rising por threshold and shuts down when the voltage on this pin drops below the falling por threshold. connect this pin directly to a +5v supply or through a series 300 ? resistor to a +12v supply. gnd - bias and reference ground for the ic. en - this pin is a threshold-sensitive enable input for the controller. connecting the 12v supply to en through an appropriate resistor divider provides a means to synchronize power-up of the controller and the mosfet driver ics. when en is driven above 1.24v, the ISL6561 is active depending on status of enll, the internal por, and pending fault states. driving en below 1.14v will clear all fault states and prime the isl6556 to soft start when re-enabled. enll - this pin is implemented in qfn ISL6561 only. it?s a logic-level enable input for the controller. when asserted to a logic high, the ISL6561 is active depending on status of en, the internal por, vid inputs and pending fault states. deasserting enll will clear all fault states and prime the ISL6561 to soft start when re-enabled. fs - a resistor, placed from fs to ground will set the switch- ing frequency. there is an inverse relationship between the value of the resistor and the switching frequency. see figure 15 and equation 29. vid4, vid3, vid2, vid1 , vid0, and vid12.5 - these are the inputs to the internal dac that provides the reference voltage for output regulation. connect these pins either to open-drain outputs with or with out external pull-up resistors or to active-pull-up output s. vid4-vid12.5 have 50ua internal pull-up current sources that diminish to zero as the voltage rises above the logic-hi gh level. these inputs can be pulled up as high as vcc plus 0.3v. vdiff, vsen, and rgnd - vsen and rgnd form the precision differential remote-sen se amplifier. this amplifier converts the differential volt age of the remote output to a single-ended voltage referenced to local ground. vdiff is the amplifier?s output and t he input to the regulation and protection circuitry. connect vsen and rgnd to the sense pins of the remote load. fb and comp - inverting input and output of the error amplifier respectively. fb is connected to vdiff through a resistor. a negative current, proportional to output current is present on the fb pin. a prop erly sized resistor between vdiff and fb sets the load line (droop). the droop scale factor is set by the ratio of the isen resistors and the lower mosfet r ds(on) . comp is tied back to fb through an external r-c network to compensate the regulator. dac and ref - the dac output pin is the output of the precision internal dac reference. the ref input pin is the positive input of the error am p. in typical applications, a 1k ? , 1% resistor is used between dac and ref to generate a precise offset voltage. this voltage is proportional to the offset current determined by the offset resistor from ofs to ground or vcc. a capacitor is used between ref and ground to smooth the voltage transition during dynamic vid? operations. pwm1, pwm2, pwm3, pwm4 - pulse-width modulation outputs. connect these pins to the pwm input pins of the intersil driver ic. the number of active channels is determined by the state of pwm3 and pwm4. tie pwm3 to vcc to configure for 2-phase operation. tie pwm4 to vcc to configure for 3-phase operation. isen1+, isen1-; isen2+, isen2-; isen3+, isen3-; isen4+, isen4- - the isen+ and isen- pins are current sense inputs to individual diff erential amplifiers.he sensed current is used as a reference for channel balancing, protection, and regulation. inactive channels should have their respective current sense inputs left open (for example, for 3-phase operation open isen4+). for dcr sensing, connect each isen- pin to the node between the rc sense elements. tie the isen+ pin to the other end of the sense capacitor through a resistor, r isen . the voltage across the sense capacitor is proportional to the inductor current. the sense current is proportional to the output current, and scaled by the dcr of the inductor, divided by r isen . when configured for r ds(on) current sensing, the isen1-, isen2-, isen3-, and isen4- pins are grounded at the lower mosfet sources. the isen 1+, isen2+, isen3+, and isen4+ pins are then held at a virtual ground, such that a resistor connected between them, and the drain terminal of the associated lower moset, will carry a current proportional to the current flowing through that channel. the current is determined by th e negative voltage developed across the lower mosfet?s r ds(on) , which is the channel current scaled by r ds(on) . pgood - pgood is used as an indication of the end of soft-start per intel vr10. it is an open-drain logic output that is low impedance until the soft start is completed. it will be pulled low again once the under-voltage point is reached. ofs - the ofs pin provides a means to program a dc offset current for generating a dc offs et voltage at the ref input. the offset current is generate d via an external resistor and precision internal voltage references. the polarity of the offset is selected by connecting the resistor to gnd or vcc. for no offset, the ofs pin should be left unterminated. tcomp - temperature compensation scaling input. a resistor from this pin to ground scales temperature compensation of internal thermal sense circuitry. the sensed temperature is utilized to modify the droop current output to fb to adjust for mosfet r ds(on) or inductor dcr variations with temperature. ISL6561
11 ovp - over-voltage protection pin. this pin pulls to vcc and is latched when an over-volta ge condition is detected. connect this pin to the gate of an scr or mosfet tied from v in or v out to ground to prevent damage to the load. this pin may be pulled above vcc as high as 15v to ground with an external resistor. however, it is only capable of pulling low when vcc is above 2v. idroop - idroop is the ouput pin of sensed average channel current which is propotional to load current. in the application which does not require loadline, leave this pin open. in the application which requires load line, connect this pin to fb so that the sensed average current will flow through the resistor between fb and vdiff to create a voltage drop which is propotional to load current. operation multi-phase power conversion microprocessor load current pr ofiles have changed to the point that the advan tages of multi-phase power conversion are impossible to ignore. the technical challenges associated with producing a single-phase converter which is both cost-effective and thermally viable have forced a change to the cost-saving appr oach of multi-phase. the ISL6561 controller helps simplifying the implementation by integrating vital functions and requiring minimal output components. the block diagrams on pages 2 and 3 provide top level views of multi-phase power conversion using the isl65556acb and ISL6561cr controllers. interleaving the switching of each channel in a multi-phase converter is timed to be symmetrically out of phase with each of the other channels. in a 3-phase converte r, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. as a result, the three-phase converter has a combined ripple frequency three times greater than the ripple frequency of any one phase. in addition, the peak-to- peak amplitude of the combined inductor currents is reduced in proportion to the number of phases (equations 1 and 2). increased ripple frequency and lower ripple amplitude mean that the designer can use less per-channel inductance and lower total output capacitance for any performance specification. figure 1 illustrates the multiplic ative effect on output ripple frequency. the three channel currents (il1, il2, and il3) combine to form the ac ripple current and the dc load current. the ripple component has three times the ripple frequency of each individual channel current. each pwm pulse is terminated 1/3 of a cycle after the pwm pulse of the previous phase. the peak-to- peak current for each phase is about 7a, and the dc components of the inductor currents combine to feed the load. to understand the reduction of ripple current amplitude in the multi-phase circuit, ex amine the equation representing an individual channel?s peak -to-peak inductor current. in equation 1, v in and v out are the input and output voltages respectively, l is the single-channel inductor value, and f s is the switching frequency. the output capacitors conduct the ripple component of the inductor current. in the case of multi-phase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. compare equation 1 to the expression for the peak-to-peak current after the summation of n symmetrically phase-shifted inductor currents in equation 2. peak-to-peak ripple current decreases by an amount proportional to the number of channels. output- voltage ripple is a function of capacitance, capacitor equivalent series resistance (esr), and inductor ripple figure 1. pwm and inductor-current waveforms for 3-phase converter 1 s/div pwm2, 5v/div pwm1, 5v/div il2, 7a/div il1, 7a/div il1 + il2 + il3, 7a/div il3, 7a/div pwm3, 5v/div i pp v in v out ? () v out lf s v in ----------------------------------------------------- - = (eq. 1) figure 2. channel input currents and input- capacitor rms current for 3-phase converter input-capacitor current, 10a/div 1 s/div channel 1 input current 10a/div channel 2 input current 10a/div channel 3 input current 10a/div ISL6561
12 current. reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. another benefit of interleaving is to reduce input ripple current. input capacitance is determined in part by the maximum input ripple current. multi-phase topologies can improve overall system cost and size by lo wering input ripple current and allowing the designer to reduce the cost of input capacitance. the example in figure 2 illustrates input currents from a three-phase converter combining to reduce the total input ripple current. the converter depicted in figure 2 delivers 36a to a 1.5v load from a 12v input. the rm s input capacitor current is 5.9a. compare this to a single-phase converter also stepping down 12v to 1.5v at 36a. the single-phase converter has 11.9a rms input capacitor current. the single-phase converter must use an input capacitor bank with twice the rms current capacity as the equivalent three- phase converter. figures 16, 17 and 18 in the section entitled input capacitor selection can be used to determine the input-capacitor rms current based on load current, duty cycle, and th e number of channels. they are provided as aids in determining the optimal input capacitor solution. figure 19 shows the single phase input-capacitor rms current for comparison. pwm operation the timing of each converter leg is set by the number of active channels. the default channel setting for the ISL6561 is four. one switching cycle is defined as the time between pwm1 pulse termination signals. the pulse termination signal is the internally generated clock signal that triggers the falling edge of pwm1. the cycle time of the pulse termination signal is the inve rse of the switching frequency set by the resistor between the fs pin and ground. each cycle begins when the clock signal commands the channel-1 pwm output to go low. the pwm1 transition signals the channel-1 mosfet driver to turn off the channel-1 upper mosfet and turn on the channel-1 synchronous mosfet. in the default channel configuration, the pwm2 pulse terminates 1/4 of a cycle af ter pwm1. the pwm3 output follows another 1/4 of a cycl e after pwm2. pwm4 terminates another 1/4 of a cycle after pwm3. if pwm3 is connected to v cc, two channel operation is selected and the pwm2 pulse terminates 1/2 of a cycle later. connecting pwm4 to vcc selects three channel operation and the pulse-termination ti mes are spaced in 1/3 cycle increments. once a pwm signal transitions low, it is held low for a minimum of 1/3 cycle. this forc ed off time is required to ensure an accurate current sample. current sensing is described in the next section. after the forced off time expires, the pwm output is enab led. the pwm output state is driven by the position of th e error amplifier output signal, v comp , minus the current correction signal relative to the sawtooth ramp as illustrated in figure 4. when the modified v comp voltage crosses the sawtooth ramp, the pwm output transitions high. the mosfet driver detects the change in state of the pwm signal, turns off the synchronous mosfet and turns on the upper mosfet. the pwm signal remains high until the pulse terminat ion signal commands the beginning of the next cycle by triggering the pwm signal low. current sensing the ISL6561 supports induct or dcr sensing or mosfet r ds(on) sensing. the internal circuitry, shown in figures 3 and 5, represents channel n of an n-channel converter. this circuitry is repeated for each channel in the converter, but may not be active depending on the status of the pwm3 and pwm4 pins, as described in the pwm operation section. mosfet r ds(on) sensing the controller can sense the channel load current by sampling the voltage across the lower mosfet r ds(on) as in figure 6. the amplifier is ground-reference by connecting the isen- input to the source of the lower mosfet. isen+ connects to the phase node through a resistor r isen . the voltage across r isen is equivalent to the voltage drop across the r ds(on) of the lower mosfet while it is conducting. the resulting current into the isen+ pin is proportional to the channel current i l . the isen current is then sampled and held after sufficient settling time as described in current sampling section. the sampled current i n , is used for channel-current balance, load-line regulation, and overcurrent protection. fr om figure 4, the following equation for i sen is derived where i l is the channel current. i l pp , v in nv out ? () v out lf s v in ----------------------------------------------------------- - = (eq. 2) figure 3. mosfet r ds(on) current-sensing circuit i n i sen i l r ds on () r isen ------------------------- - = - + isen+(n) r isen sample & hold ISL6561 internal circuit external circuit v in n-channel mosfets - + i l r ds on () i l isen-(n) (ptc) i sen i l r ds on () r isen ---------------------- = (eq. 3) ISL6561
13 inductor dcr sensing an inductor has a distributed direct current winding resistance (dcr). consider the inductor dcr as a separate lumped quantity as shown in figure 4. the channel current, i l , flowing through the inductor, also passes through the dcr. equation 4 shows the s-domain equivalent voltage, v l , across the inductor. a simple r-c network across the inductor extracts the dcr voltage, as shown in figure 5. the voltage on the capacitor, v c , can be shown to be proportional to the channel current i l (see equation 5). if the r-c network components are selected such that the r- c time constant matches the inductor l/dcr time constant, then v c is equal to the voltage drop across the dcr. the capacitor voltage, v c , is replicated across the sense resistor r isen . so that the current flowing through the sense resistor is proportional to the inductor current. equation 6 shows that the relationship between the channel current and the sensed current i sen , is driven by the value of the sense resistor and the inductor dcr. current sampling during the forced off-time following a pwm transition low, the associated channel current sense amplifier reproduces a signal , i sen , proportional to the inductor current, i l . regardless of the current sense method, i sen is simply a scaled version of the inductor current. coincident with the falling edge of the pwm signal, the sample and hold circuitry samples i sen . this is illustrated in figure 5. the sample time, t samp , is fixed and equal to 1/3 of the switching period, t sw . therefore, the sample current, i n , is proportional to the output current and held for one switching cycle. the sample current is used for current balance, load-line regulation, and overcurrent protection. channel-current balance the sampled currents i n , from each active channel are summed together and divided by the number of active channels. the resulting cycle average current, i avg , provides a measure of the to tal load current demand on the converter during each switching cycle. channel current balance is achieved by comparing the sampled current of each channel to the cycle average current, and making an appropriate adjustment to ea ch channel pulse width based on the error. intersil?s patented current-balance method is illustrated in figure 6, with error correction for channel 1 represented. in the figure, the cycle average current combines with the channel 1 sample, i 1 , to create an error signal i er . the filtered error signal modifies the pulse width commanded by v comp to correct any unbalance and force i er toward zero. the same method for error signal correction is applied to each active channel. v l i l sl dcr + ? () ? = (eq. 4) v c s l dcr ------------- ? 1 + ?? ?? dcr i l ? () ? src 1 + ? () -------------------------------------------------------------------- - = (eq. 5) figure 4. dcr sensing configuration i n i sen i l dcr r isen ------------------- = - + isen- sample & hold ISL6561 internal circuit v in isen+ pwm(n) ISL6561 r isen dcr l inductor r v out c out - + v c (s) c i l s () - + v l i sen i l dcr r isen ----------------- - ? = (eq. 6) t samp t sw 3 ---------- 1 3f sw ? ------------------ == (eq. 7) figure 5. sample and hold timing time pwm i l switching period i sen sample current, i n t samp ISL6561
14 channel current balance is essential in realizing the thermal advantage of multi-phase operat ion. the heat generated in down converting is dissipated over multiple devices and a greater area. the designer avoids the complexity of driving multiple parallel mosfets, and the expense of using heat sinks and nonstandard magnetic materials. voltage regulation the integrating compensation network shown in figure 7 assures that the steady-state e rror in the output voltage is limited only to the error in t he reference voltage (output of the dac) and offset errors in the ofs current source, remote-sense and error amplifiers. intersil specifies the guaranteed tolerance of the ISL6561 to include the combined tolerances of each of these elements. the output of the e rror amplifier, v comp , is compared to the sawtooth waveform to generate the pwm signals. the pwm signals control the timing of the intersil mosfet drivers and regulate the converter output to the specified reference voltage. the internal and extern al circuitry that controls voltage regulation is illustrated in figure 7. the ISL6561 incorporates an internal differential remote- sense amplifier in the feedback path. the amplifier removes the voltage error encountered when measuring the output voltage relative to the local controller ground reference point resulting in a more accurate means of sensing output voltage. connect the micropro cessor sense pins to the non- inverting input, vsen, and inverting input, rgnd, of the remote-sense amplifier. th e remote-sense output, v diff , is connected to the inverting input of the error amplifier through an external resistor. a digital to analog converter (dac) generates a reference voltage based on the state of logic signals at pins vid4 through vid12.5. the dac decodes the a 6-bit logic signal (vid) into one of the discrete voltages shown in table 1. each vid input offers a 50 a pull-up to an internal 2.5v source for use with open-drain outputs. the pull-up current diminishes to zero above the logic threshold to protect voltage-sensitive output device s. external pull-up resistors can augment the pull-up current sources in case leakage into the driving device is greater than 50 a. load-line regulation some microprocessor manufacturers require a precisely- controlled output resistance. this dependence of output voltage on load current is often termed ?droop? or ?load line? regulation. by adding a well controlled output impedance, the output voltage can effectiv ely be level shifted in a direction which works to achieve the load-line regulation required by these manufacturers. figure 6. channel-1 pwm function and current- balance adjustment n i avg i 4 * i 3 * i 2 - + + - + - f(j ) pwm1 i 1 v comp sawtooth signal i er note: *channels 3 and 4 are optional. filter figure 7. output voltage and load-line regulation with offset adujustment i avg external circuit ISL6561 internal circuit comp r c r fb fb vdiff vsen rgnd - + v droop error amplifier - + v out + differential remote-sense amplifier v comp c c ref dac r ref c ref - + v out - idroop table 1. voltage identification (vid) codes vid4 vid3 vid2 vid1 vid0 vid12.5 vdac 0 1 0 1 0 0 0.8375v 0 1 0 0 1 1 0.8500v 0 1 0 0 1 0 0.8625v 0 1 0 0 0 1 0.8750v 0 1 0 0 0 0 0.8875v 0 0 1 1 1 1 0.9000v 0 0 1 1 1 0 0.9125v 0 0 1 1 0 1 0.9250v 0 0 1 1 0 0 0.9375v 0 0 1 0 1 1 0.9500v 0 0 1 0 1 0 0.9625v 0 0 1 0 0 1 0.975v0 0 0 1 0 0 0 0.9875v 0 0 0 1 1 1 1.0000v 0 0 0 1 1 0 1.0125v 0 0 0 1 0 1 1.0250v 0 0 0 1 0 0 1.0375v 0 0 0 0 1 1 1.0500v ISL6561
15 in other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. droop can help to control t he output-voltage spike that results from fast load-current demand changes. the magnitude of the spike is dictated by the esr and esl of the output capaci tors selected. by positioning the no-load voltage level near the upper specification limit, a larger negative spike can be sustained without crossing the lower limit. by adding a well controlled output impedance, the output voltage under load can effectively be level shifted down so that a larger positive spike can be sustained without crossing the upper specification limit. as shown in figure 8, a current proportional to the average current in all active channels, i avg , flows from fb through a load-line regulation resistor, r fb . the resulting voltage drop across r fb is proportional to the output current, effectively creating an output voltage dro op with a steady-state value defined as the regulated output voltage is reduced by the droop voltage v droop . the output voltage as a function of load current is derived by combining equations 8 with the appropriate sample current expression defined by the current sense method employed. where v ref is the reference voltage, v ofs is the programmed offset voltage, v out is the total output current of the converter, r isen is the sense resistor in the isen line, and r fb is the feedback resistor. r x has a value of dcr, r ds(on) , or r sense depending on the sensing method. output-voltage offset programming the ISL6561 allows the designer to accurately adjust the offset voltage. when a resistor, r ofs , is connected between ofs and vcc, the voltage across it is regulated to 2.0v. this causes a proportional current (i ofs ) to flow into ofs. if r ofs is connected to ground, the voltage across it is regulated to 0.5v, and i ofs flows out of ofs. a resistor 0 0 0 0 1 0 1.0625v 0 0 0 0 0 1 1.0750v 0 0 0 0 0 0 1.0875v 1111 1 1 off 1111 1 0 off 1 1 1 1 0 1 1.1000v 1 1 1 1 0 0 1.1125v 1 1 1 0 1 1 1.1250v 1 1 1 0 1 0 1.1375v 1 1 1 0 0 1 1.1500v 1 1 1 0 0 0 1.1625v 1 1 0 1 1 1 1.1750v 1 1 0 1 1 0 1.1875v 1 1 0 1 0 1 1.2000v 1 1 0 1 0 0 1.2125v 1 1 0 0 1 1 1.2250v 1 1 0 0 1 0 1.2475v 1 1 0 0 0 1 1.2500v 1 1 0 0 0 0 1.2625v 1 0 1 1 1 1 1.2750v 1 0 1 1 1 0 1.2875v 1 0 1 1 0 1 1.3000v 1 0 1 1 0 0 1.3125v 1 0 1 0 1 1 1.3250v 1 0 1 0 1 0 1.3375v 1 0 1 0 0 1 1.3500v 1 0 1 0 0 0 1.3625v 1 0 0 1 1 1 1.3750v 1 0 0 1 1 0 1.3875v 1 0 0 1 0 1 1.4000v 1 0 0 1 0 0 1.4125v 1 0 0 0 1 1 1.4250v 1 0 0 0 1 0 1.4375v 1 0 0 0 0 1 1.4500v 1 0 0 0 0 0 1.4625v 0 1 1 1 1 1 1.4750v 0 1 1 1 1 0 1.4875v 0 1 1 1 0 1 1.5000v 0 1 1 1 0 0 1.5125v 0 1 1 0 1 1 1.5250v table 1. voltage identification (vid) codes (continued) vid4 vid3 vid2 vid1 vid0 vid12.5 vdac 0 1 1 0 1 0 1.5375v 0 1 1 0 0 1 1.5500v 0 1 1 0 0 0 1.5625v 0 1 0 1 1 1 1.5750v 0 1 0 1 1 0 1.5875v 0 1 0 1 0 1 1.600v table 1. voltage identification (vid) codes (continued) vid4 vid3 vid2 vid1 vid0 vid12.5 vdac v droop i avg r fb = (eq. 8) v out v ref v offset ? i out 4 ------------- r x r isen ----------------- -r fb ?? ?? ?? ? = (eq. 9) ISL6561
16 between dac and ref, r ref , is selected so that the product (i ofs x r ref ) is equal to the desired offset voltage. these functions are shown in figures 8. as evident in figure 8, the ofsout pin must be connected to the ref pin for this curre nt injection to function in ISL6561cr. the current flowing through r ref creates an offset at the ref pin, which is ultimately duplicated at the output of the regulator. once the desired output offset voltage has been determined, use the following formulas to set r ofs : for positive offset (connect r ofs to vcc): for negative offset (connect r ofs to gnd): dynamic vid modern microprocessors need to make changes to their core voltage as part of norma l operation. they direct the core-voltage regulator to do this by making changes to the vid inputs during regulator operation. the power management solution is required to monitor the dac inputs and respond to on-the-fly vid changes in a controlled manner. supervising the safe output voltage transition within the dac range of the processo r without discontinuity or disruption is a necessary function of the core-voltage regulator. the ISL6561 checks the vid inputs six times every switching cycle. if the vid code is found to have has changed, the controller waits half of a complete cycle before executing a 12.5mv change. if during the hal f-cycle wait period, the difference between dac level and the new vid code changes, no change is made. if the vid code is more than 1 bit higher or lower than the dac (not recommended), the controller will execute 12.5mv changes six times per cycle until vid and dac are equal. it is for this reason that it is important to carefully control the rate of vid stepping in 1- bit increments. in order to ensure the smooth transition of output voltage during vid change, a vid step change smoothing network composed of r ref and c ref is required for an ISL6561 based voltage regulator. the selection of r ref is based on the desired offset as detailed above in output-voltage offset programming . the selection of c ref is based on the time duration for 1 bit vid change and the allowable delay time. assuming the microprocessor co ntrols the vid change at 1 bit every t vid , the relationship between the time constant of r ref and c ref network and t vid is given by equation 12. typically r ref is selected to be 1k ? , so with a vid step change rate of 5 s per bit, the value of c ref is 22nf based on equation 12. temperature compensation both the mosfet r ds(on) and inductor dcr of inductor vary in proportion to varying temperature. this means that a circuit using r ds(on) or dcr to sense channel current is subject to a corresponding error in current measurement. in order to compensate for this temperature-related error, a temperature compensation circuit is provided within ISL6561. this circuit senses t he internal ic temperature and, based on a resistor-selectable scaling factor, adjust the droop current ouput to the idroop pin. when the tcomp resistor is properly selected, the droop current can accurately represent the load current to achieve a linear, temperature-independant load line. the value of the tcomp resistor can be determined using equation 13. in equation 13, k t is the temperature coupling coefficient between the ISL6561 and the lower mosfet or output inductor. it represents how closel y the controller temperature dynamic vid d/a e/a vcc dac fb ref ofs vcc gnd + - + - 0.5v 2.0v or gnd r ofs r ref ISL6561cr figure 8. output voltage offset programming with ISL6561cr r ofs 2r ref v offset -------------------------- = (eq. 10) r ofs 0.5 r ref v offset ------------------------------ = (eq. 11) c ref r re f 4t vid = (eq. 12) (eq. 13) r tcomp k t k tc --------------------- - = ISL6561
17 tracks the lower mosfet or inductor temperature. the value of k t is typically between 75% and100%. k tc is the temperature dependant transconductance of internal compensation circuit. its vaule is designed as 1 a/v/c. the temperature coefficient of mosfet r ds(on) or inductor dcr is given by . this is the ratio of the change in resistance and the change in temperature. resistance is normalized to the value at 25c and the value of is typically between 0.35%/c and 0.50%/c. for copper wound inductors, is 0.39%/c. according to equation 13, a voltage regulator with 80% thermal coupling coefficient bet ween the controller and lower mosfet and 0.4% /c temperature coefficient of mosfet r ds(on) requires a 5k ? tcomp resistor. initialization prior to converter initialization, proper conditions must exist on the enable inputs and vcc. wh en the conditions are met, the controller begins soft-star t. once the output voltage is within the proper window of operation, pgood asserts logic 1. enable and disable while in shutdown mode, the pwm outputs are held in a high-impedance state to assure the drivers remain off. the following input conditions must be met before the ISL6561 is released from shutdown mode. 1 - the bias voltage applied at vcc must reach the internal power-on reset (por) rising threshold. once this threshold is reached, proper operation of all aspects of the ISL6561 is guaranteed. hysteresis betwe en the rising and falling thresholds assure that once enabled, the ISL6561 will not inadvertently turn off unless the bias voltage drops substantially (see electrical specifications ). 2 - the ISL6561 features an enable input (en) for power sequencing between the controller bias voltage and another voltage rail. the enable com parator holds the ISL6561 in shutdown until the voltage at en rises above 1.24v. the enable comparator has about 100mv of hysteresis to prevent bounce. it is important that the driver ics reach their por level before the ISL6561 becomes enabled. the schematic in figure 9 demo nstrates sequencing the ISL6561 with the hip660x family of intersil mosfet drivers, which require 12v bias. 3 - the voltage on enll must be logic high to enable the controller. this pin is typically connected to the vid_pgood. 4 - the vid code must not be 111111 or 111110. these codes signal the controller th at no load is present. the controller will enter shut-down m ode after receiving either of these codes and will execute soft start upon receiving any other code. these codes can be used to enable or disable the controller but it is not re commended. after receiving one of these codes, the controller executes a 2-cycle delay before changing the over-voltage trip level to the shut-down level and disabling pwm. over-voltage shutdown cannot be reset using one of these codes. to enable the controller, vcc must be greater than the por threshold; the voltage on en must be greater than 1.24v; for ISL6561cr, enll must be logic high; and vid cannot be equal to 111111 or 111110. when each of these conditions is true, the controller imme diately begins the soft-start sequence. soft-start during soft start, th e dac voltage ramps linearly from zero to the programmed vid level as shown in figure 10. the pwm signals remain in the high-impedance st ate until the controller detects that the ramping dac level has reached the output-voltage level. this protects the system against the large, negative inductor current s that would otherwise occur when starting with a pre-existing charge on the output as the controller attempted to regulate to zero volts at the beginning of the soft-start cycle. the soft-start time, t ss , begins with a delay period equal to 64 switching cycles followed by a linear ramp with a rate determined by the switching period, 1/f sw . figure 9. power sequencing using threshold- sensitive enable (en) function - + 1.24v external circuit ISL6561 internal circuit en +12v por circuit 10.7k ? 1.40k ? enable comparator soft start and fault logic enll vcc t ss 64 1280 vid ? + f sw ----------------------------------------- = (eq. 14) ISL6561
18 for example, a regulator with 250khz switching frequency having vid set to 1.35v has t ss equal to 6.912ms. a 100mv offset exists on the remote-sense amplifier at the beginning of soft start and ramps to zero during the first 640 cycles of soft start (704 cycl es following enable). this prevents the large inrush current that would otherwise occur should the output voltage star t out with a slight negative bias. during the first 640 cycles of soft start (704 cycles following enable) the dac voltage increments the reference in 25mv steps. the remainder of soft start sees the dac ramping with 12.5mv steps. fault monitoring and protection the ISL6561 actively monitors output voltage and current to detect fault conditions. fault monitors trigger protective measures to prevent damage to a microprocessor load. one common power good indicator is provided for linking to external system monitors. th e schematic in figure 11 outlines the interaction between the fault monitors and the power good signal. power good signal the power good pin (pgood) is an open-drain logic output that transitions high when t he converter is operating after soft start. pgood pulls low during shutdown and releases high after a successf ul soft start. pgood only transitions low when an under-voltage condition is detected or the controller is disabled by a reset from en, enll, por, or one of the no-cpu vid codes. after an under voltage event, pgood will return high unless the controller has been disabled. pgood does not auto matically transition low upon detection of an over-voltage condition. under-voltage detection the under-voltage threshold is set at 75% of the vid code. when the output volt age at vsen is belo w the under-voltage threshold, pgood gets pulled low. over-voltage protection when vcc is above 1.4v, but otherwise not valid as defined under power on reset in electrical specifications , the over- voltage trip circuit is active us ing auxiliary circuitry. in this state, an over-voltage trip occurs if the voltage at vsen exceeds 1.8v. with valid vcc, the over-volt age circuit is sensitive to the voltage at vdiff. in this state, the trip level is 1.7v prior to valid enable conditions being met as described in enable and disable . the only exception to this is when the ic has been disabled by an over-voltage trip. in that case the over- voltage trip point is vid plus 200mv. during soft start, the over-voltage trip level is the higher of 1.7v or vid plus 200mv. upon successful soft start, the over-voltage trip level is 200mv above vid. two acti ons are taken by the ISL6561 to protect the microprocessor load when an over-voltage condition occurs. at the inception of an over-v oltage event, all pwm outputs are commanded low until the voltage at vsen falls below 0.6v with valid vcc or 1.5v otherwise. this causes the intersil drivers to turn on the lower mosfets and pull the output voltage below a level that might cause damage to the load. the pwm outputs remain low until vdiff falls to the programmed dac level when they enter a high-impedance state. the intersil drivers respond to the high-impedance input by turning off both upper and lower mosfets. if the over-voltage condition reoccurs, the ISL6561 will again figure 10. soft-start waveforms with an un-biased output. fsw = 500khz vout, 500mv/div en, 5v/div 500 s/div figure 11. power good and protection circuitry ovp - + vid + 0.2v vdiff - + 100 a i avg - + dac reference ov oc uv pgood 75% soft start, fault and control logic - + oc i 1 repeat for each channel 100 a ISL6561
19 command the lower mosfets to turn on. the ISL6561 will continue to protect the load in this fashion as long as the over-voltage condition recurs. simultaneous to the protective action of the pwm outputs, the ovp pin pulls to vcc delivering up to 100ma to the gate of a crowbar mosfet or scr pl aced either on the input rail or the output rail. turning on the mosfet or scr collapses the power rail and causes a fuse placed further up stream to blow. the fuse must be sized such that the mosfet or scr will not overheat before the fuse blows. the ovp pin is tolerant to 12v (see absolute maximum ratings ), so an external resistor pull up can be used to augment the driving capability. if using a pull up resi stor in conjunction with the internal over-voltage protection function, care must be taken to avoid nuisance trips that could occur when vcc is below 2v. in that case, the controller is incapable of holding ovp low. once an over-voltage condition is detected, normal pwm operation ceases until the ISL6561 is reset. cycling the voltage on en or enll or vcc below the por-falling threshold will reset the controller. cycling the vid codes will not reset the controller. over-current protection ISL6561 has two levels of ov er-current protection. each phase is protected from a sustained over-current condition on a delayed basis, while the combined phase currents are protected on an in stantaneous basis. in instantaneous protecti on mode, the ISL6561 takes advantage of the proportionality between the load current and the average current, i avg to detect an over-current condition. see the channel-current balance section for more detail on how the average current is measured. the average current is continually compared with a constant 100 a reference current as shown in figure 11. once the average current exceeds the reference current, a comparator triggers the converter to shutdown. in individual over-current protection mode, the ISL6561 continuously compares the current of each channel with the same 100 a reference current. if any channel current exceeds the reference current continuously for eight consecutive cycles, the comparator triggers the converter to shutdown. at the beginning of over-curre nt shutdown, the controller places all pwm signals in a high-impedance state commanding the intersil mosfet driver ics to turn off both upper and lower mosfets. the system remains in this state a period of 4096 switchin g cycles. if the controller is still enabled at the end of this wait period, it will attempt a soft start. if the fault remains, trip-retry cycles continue indefinitely (as shown in figure 12) until either controller is disabled or the fault is cl eared. note that the energy delivered during trip-retry cycl ing is much less than during full-load operation, so there, there is no thermal hazard during this kind of operation. general design guide this design guide is intended to provide a high-level explanation of the steps neces sary to create a multi-phase power converter. it is assumed that the reader is familiar with many of the basic skills and te chniques referenced below. in addition to this guide, intersil provides complete reference designs that include schematics, bills of materials, and example board layouts for all common microprocessor applications. power stages the first step in designing a multi-phase converter is to determine the number of phases. this determination depends heavily on the cost analysis which in turn depends on system constraints that differ from one design to the next. principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board; whether through-hole components are permitted; and the total board space available for power-supply circuitry. generally speaking, the most economical solutions are those in which each phase handles between 15 and 20a. all surface-mount designs will tend toward the lower end of this current range. if through-hole mosfets and inductors can be used, higher per-phase currents are possible. in cases where board space is the limiting constraint, current may be pushed above 30a per phase, but these designs require heat sinks and forced air to cool the mosfets, inductors and heat-dissipating surfaces. mosfets the choice of mosfets depends on the current each mosfet will be required to conduct; the switching frequency; the capability of the mosfets to dissipate heat; and the availability and nature of heat sinking and air flow. 0a 0v 2ms/div output current, 50a/div figure 12. overcurrent behavior in hiccup mode. f sw = 500khz output voltage, 500mv/div ISL6561
20 lower mosfet power calculation the calculation for heat dissipated in the lower mosfet is simple, since virtually all of the heat loss in the lower mosfet is due to current conducted through the channel resistance (r ds(on) ). in equation 15, i m is the maximum continuous output current; i pp is the peak-to-peak inductor current (see equation 1); d is the duty cycle (v out /v in ); and l is the per-channel inductance. an additional term can be added to the lower-mosfet loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-mosfet body diode. this term is dependent on the diode forward voltage at i m , v d(on) ; the switching frequency, f s ; and the length of dead times, t d1 and t d2 , at the beginning and the end of the lower-mosfet conduction interval respectively. thus the total maximum power dissipated in each lower mosfet is approximated by the summation of p low,1 and p low,2 . upper mosfet power calculation in addition to r ds(on) losses, a large portion of the upper- mosfet losses are due to currents conducted across the input voltage (v in ) during switching. since a substantially higher portion of the upper-mosfet losses are dependent on switching frequency, the power calculation is more complex. upper mosfet loss es can be divided into separate components involving the upper-mosfet switching times; the lower-mo sfet body-diode reverse- recovery charge, q rr ; and the upper mosfet r ds(on) conduction loss. when the upper mosfet turns off, the lower mosfet does not conduct any portion of the inductor current until the voltage at the phase node falls below ground. once the lower mosfet begins conducting, the current in the upper mosfet falls to zero as the current in the lower mosfet ramps up to assume the full inductor current. in equation 17, the required time for this commutation is t 1 and the approximated associated power loss is p up,1 . at turn on, the upper mosfet begins to conduct and this transition occurs over a time t 2 . in equation 18, the approximate power loss is p up,2 . a third component involves the lower mosfet?s reverse- recovery charge, q rr . since the inductor current has fully commutated to the upper mosfet before the lower- mosfet?s body diode can draw all of q rr , it is conducted through the upper mosfet across vin. the power dissipated as a result is p up,3 and is approximately finally, the resistive part of t he upper mosfet?s is given in equation 19 as p up,4 . the total power dissipated by the upper mosfet at full load can now be approximated as the summation of the results from equations 17, 18, 19 and 20. since the power equations depend on mosfet parameters, choosing the correct mosfets can be an iterative process involving repetitive solutions to the loss equations for different mosfets and different switching frequencies. current sensing resistor the resistors connected be tween these pins and the respective phase nodes determine the gains in the load-line regulation loop and the channel-current balance loop as well as setting the over-current trip point. select values for these resistors based on the room temperature r ds(on) of the lower mosfets, dcr of inductor or additional resistor; the full-load operating current, i fl ; and the number of phases, n using equation 21. in certain circumstances, it may be necessary to adjust the value of one or more isen resistor. when the components of one or more channels are inhibited from effectively dissipating their heat so that the affected channels run hotter than desired, chose new, smaller values of r isen for the affected phases (see the section entitled channel-current balance ). choose r isen,2 in proportion to the desired decrease in temperature rise in order to c ause proportionally less current to flow in the hotter phase. p low 1 , r ds on () i m n ----- - ?? ?? ?? 2 1d ? () i lpp , 2 1d ? () 12 -------------------------------- + = (eq. 15) p low 2 , v don () f s i m n ----- - i pp 2 -------- - + ?? ?? t d1 i m n ----- - i pp 2 -------- - ? ?? ?? ?? t d2 + = (eq. 16) p up 1 , v in i m n ----- - i pp 2 -------- - + ?? ?? t 1 2 ---- ?? ?? ?? f s (eq. 17) p up 2 , v in i m n ----- - i pp 2 -------- - ? ?? ?? t 2 2 ---- ?? ?? ?? f s (eq. 18) p up 3 , v in q rr f s = (eq. 19) p up 4 , r ds on () i m n ----- - ?? ?? ?? 2 d i pp 2 12 --------- - + (eq. 20) r isen r x 70 10 6 ? ----------------------- i fl n ------- - = (eq. 21) r isen 2 , r isen ? t 2 ? t 1 ---------- = (eq. 22) ISL6561
21 in equation 22, make sure that ? t 2 is the desired temperature rise above the ambient temperature, and ? t 1 is the measured temperature rise above the am bient temperature. while a single adjustment according to equation 22 is usually sufficient, it may occasionally be necessary to adjust r isen two or more times to achieve optimal thermal balance between all channels. load-line regulation resistor the load-line regulation resistor is labeled r fb in figure 7. its value depends on the desired full-load droop voltage (v droop in figure 7). if equation 21 is used to select each isen resistor, the load-line regulation resistor is as shown in equation 23. if one or more of the isen re sistors is adjusted for thermal balance, as in equation 23, the load-line regulation resistor should be selected according to equation 24 where i fl is the full-load operating current and r isen(n) is the isen resistor connected to the n th isen pin. compensation the two opposing goals of compensating the voltage regulator are stability and speed. depending on whether the regulator employs the optiona l load-line regulation as described in load-line regulati on, there are two distinct methods for achieving these goals. compensating load-line regulated converter the load-line regulated converter behaves in a similar manner to a peak-current mode controller because the two poles at the output-filter l- c resonant frequency split with the introduction of current information into the control loop. the final location of these poles is determined by the system function, the gain of the current signal, and the value of the compensation components, r c and c c . since the system poles and zero are effected by the values of the components that are me ant to compensate them, the solution to the system equatio n becomes fairly complicated. fortunately there is a simple approximation that comes very close to an optimal solution. tr eating the system as though it were a voltage-mode regulator by compensating the l-c poles and the esr zero of t he voltage-mode approximation yields a solution that is always stable with very close to ideal transient performance. the feedback resistor, r fb , has already been chosen as outlined in load-line regulation resistor . select a target bandwidth for the compensated system, f 0 . the target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per- channel switching frequency. the values of the compensation components depend on the relationships of f 0 to the l-c pole frequency and the esr zero frequency. for each of the three cases which follow, there is a separate set of equations for the compensation components. in equations 25, l is the per-channel filter inductance divided by the number of active channels; c is the sum total of all output capacitors; esr is the equivalent-series resistance of the bulk output-filter capacitance; and v pp is the peak-to-peak sawtooth signal amplitude as described in figure 6 and electrical specifications . r fb v droop 70 10 6 ? ------------------------ - = (eq. 23) r fb v droop i fl r ds on () -------------------------------- r isen n () n = (eq. 24) figure 13. compensation configuration for load-line regulated ISL6561 circuit ISL6561 comp c c r c r fb fb idroop vdiff - + v droop c 2 (optional) 1 2 lc ------------------- f 0 > r c r fb 2 f 0 v pp lc 0.75v in ----------------------------------- - = c c 0.75v in 2 v pp r fb f 0 ------------------------------------ = case 1: 1 2 lc ------------------- f 0 1 2 c esr () ----------------------------- - < r c r fb v pp 2 () 2 f 0 2 lc 0.75 v in -------------------------------------------- = c c 0.75v in 2 () 2 f 0 2 v pp r fb lc ------------------------------------------------------------- = case 2: (eq. 25) f 0 1 2 c esr () ----------------------------- - > r c r fb 2 f 0 v pp l 0.75 v in esr () ------------------------------------------ = c c 0.75v in esr () c 2 v pp r fb f 0 l ------------------------------------------------- = case 3: ISL6561
22 the optional capacitor c 2 , is sometimes needed to bypass noise away from the pwm comparator (see figure 13). keep a position available for c 2 , and be prepared to install a high- frequency capacitor of between 22pf and 150pf in case any leading-edge jitter problem is noted. nce selected, the compensation values in equations 23 assure a stable converter with reasonable transient performance. in most cases, transient performance can be improved by making adjustments to r c . slowly increase the value of r c while observing the transient performance on an oscilloscope until no further im provement is noted. normally, c c will not need adjustment. keep the value of c c from equations 23 unless some performance issue is noted. the optional capacitor c 2 , is sometimes needed to bypass noise away from the pwm comparator (see figure 12). keep a position available for c 2 , and be prepared to install a high- frequency capacitor of between 22pf and 150pf in case any trailing edge jitter problem is noted. compensation without load-line regulation the non load-line regulated converter is accurately modeled as a voltage-mode regulator with two poles at the l-c resonant frequency and a zero at the esr frequency. a type iii controller, as shown in figure 14, provides the necessary compensation. the first step is to choose the desired bandwidth, f 0 , of the compensated system. choose a frequency high enough to assure adequate transient performance but not higher than 1/3 of the switching frequency. the type-iii compensator has an extra high-frequency pole, f hf . this pole can be used for added noise rejection or to assure adequate attenuation at the error- amplifier high-order pole and zero frequencies. a good general rule is to chose f hf = 10f 0 , but it can be higher if desired. choosing f hf to be lower than 10f 0 can cause problems with too much phase shift below the system bandwidth. in the solutions to the compensation equations, there is a single degree of freedom. for the solutions presented in equations 26, r fb is selected arbitrarily. the remaining compensation components are then selected according to equations 26. in equations 26, l is the per-channel filter inductance divided by the number of active channels; c is the sum total of all output capacitors; esr is the equivalent-series resistance of the bulk output-filter capacitance; and v pp is the peak-to-peak sawtooth signal amplitude as described in figure 6 and electrical specifications . output filter design the output inductors and the ou tput capacitor bank together form a low-pass filter respon sible for smoothing the pulsating voltage at the phase nodes. t he output filter also must provide the transient energy un til the regulator can respond. because it has a low bandwidth compared to the switching frequency, the outpu t filter necessarily limits the system transient response. the output c apacitor must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. in high-speed converters, the output capacitor bank is usually the most costly (and of ten the largest) part of the circuit. output filter design begins with minimizing the cost of this part of the circuit. the critical load parameters in choosing the output capacitors are the maximum size of the load step, ? i; the load-current slew rate, di/dt; and the maximum allowable output-voltage deviation under transient loading, ? v max . capacitors are characterized according to their capacitance, esr, and esl (equivalent series inductance). at the beginning of the load tr ansient, the output capacitors supply all of the transient cu rrent. the output voltage will initially deviate by an amoun t approximated by the voltage drop across the esl. as the load current increases, the voltage drop across the esr in creases linearly until the load current reaches its final value. the capacitors selected must have sufficiently low esl and esr so that the total output- figure 14. compensation circuit for ISL6561 based converter without load-line regulation ISL6561 comp c c r c r fb fb idroop vdiff c 2 c 1 r 1 c c 0.75v in 2 f hf lc 1 ? ?? ?? 2 () 2 f 0 f hf lcr fb v pp ------------------------------------------------------------------ - = r c v pp 2 ?? ?? 2 f 0 f hf lcr fb 0.75 v in 2 f hf lc 1 ? ?? ?? -------------------------------------------------------------------- - = r 1 r fb c esr () lc c esr () ? ---------------------------------------- - = c 1 lc c esr () ? r fb ---------------------------------------- - = c 2 0.75v in 2 () 2 f 0 f hf lcr fb v pp ------------------------------------------------------------------ - = (eq. 26) ISL6561
23 voltage deviation is less than the allowable maximum. neglecting the contribution of i nductor current and regulator response, the output voltage initially deviates by an amount the filter capacitor must have sufficiently low esl and esr so that ? v < ? v max . most capacitor soluti ons rely on a mixture of high-frequency capacitors with relatively low capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. minimizing the esl of the high-frequency capacitors allows them to support the output voltage as the current increase s. minimizing the esr of the bulk capacitors allows them to supply the increased current with less output voltage deviation. the esr of the bulk capacitors also creates the majority of the output-voltage ripple. as th e bulk capacitors sink and source the inductor ac ripple current (see interleaving and equation 2), a voltage develops across the bulk-capacitor esr equal to i c,p p (esr). thus, once the output capacitors are selected, the maximum allowable ripple voltage, v pp(max) , determines the lower limit on the inductance. since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. the output inductors must be capable of assuming the entire load current before the output voltage decreases more than ? v max . this places an upper limit on inductance. equation 29 gives the upper limit on l for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. equation 30 addresses the leading edge. normally, the trailing edge dictates the selection of l because duty cycles are usually less than 50%. nevertheless, both inequalities should be evaluated, and l should be selected based on the lower of the two results. in each equation, l is the per-channel inductance, c is the total output capacitance, and n is the number of active channels. input supply voltage selection the vcc input of the ISL6561 can be connected either directly to a +5v supply or th rough a current limiting resistor to a +12v supply. an integrated 5.8v shunt regulator maintains the voltage on the vcc pin when a +12v supply is used. a 300 ? resistor is suggested for limiting the current into the vcc pin to a worst-ca se maximum of approximately 25ma. switching frequency there are a number of variables to consider when choosing the switching frequency, as ther e are considerable effects on the upper-mosfet loss calcul ation. these effects are outlined in mosfets , and they establish the upper limit for the switching frequency. the lowe r limit is established by the requirement for fast transi ent response and small output- voltage ripple as outlined in output filter design . choose the lowest switching frequency that allows the regulator to meet the transient-re sponse requirements. switching frequency is determi ned by the selection of the frequency-setting resistor, r t (see the figures labeled typical application on pages 3 and 6). figure 15 and equation 31 are provided to assist in selecting the correct value for r t . input capacitor selection the input capacitors are responsible for sourcing the ac component of the input curr ent flowing into the upper mosfets. their rms current capa city must be sufficient to handle the ac component of the current drawn by the upper mosfets which is related to duty cycle and the number of active phases. ? v esl () di dt ---- - esr ()? i + (eq. 27) l esr () v in nv out ? ?? ?? v out f s v in v pp max () ----------------------------------------------------------- - (eq. 28) l 2ncv o ? i () 2 --------------------- ? v max ? i esr () ? (eq. 29) l 1.25 () nc ? i () 2 ------------------------- - ? v max ? iesr () ? v in v o ? ?? ?? (eq. 30) figure 15. r t vs switching frequency 100 1000 10000 10 switching frequency (khz) 10 100 1000 r t (k ? ) r t 1.0203 10 () 10.6258- 1.03167 () f s () log [] 1200 ? = (eq. 31) ISL6561
24 for a two phase design, use figure 16 to determine the input-capacitor rms current requirement given the duty cycle, maximum sustained output current (i o ), and the ratio of the per phase peak-to-peak inductor current (i l,pp ) to i o . select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the rms current calcul ated. the voltage rating of the capacitors should also be at least 1.25 times greater than the maximum input voltage. figures 17 and 18 provide the same input rms current information for three and four phase designs respectively. use the same approach to selecting the bulk capacitor type and number as described above. low capacitance, high-frequency ceramic capacitors are needed in addition to the bulk capacitors to suppress leading and falling edge voltage spikes. the result from the high current slew rates produced by the upper mosfets turn on and off. select low esl ceramic capacitors and place one as close as possible to each upper mosfet drain to minimize board parasitic impedances and maximize suppression. multi-phase rms improvement figure 19 is provided as a reference to demonstrate the dramatic reductions in input- capacitor rms current upon the implementation of the multi-pha se topology. for example, compare the input rms current requirements of a two-phase converter versus that of a single phase. assume both converters have a duty cycle of 0.25, maximum sustained output current of 40a, and a ratio of i c,pp to i o of 0.5. the single phase converter would require 17.3 arms current capacity while the two-phase converter would only require 10.9 arms. the advantages become even more pronounced when output current is increas ed and additional phases are added to keep the component cost down relative to the single phase approach. 0.3 0.1 0 0.2 input-capacitor current (i rms / i o ) figure 16. normalized input-capacitor rms current vs duty cycle for 2-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v in / v o ) i l,pp = 0 i l,pp = 0.5 i o i l,pp = 0.75 i o duty cycle (v in / v o ) figure 17. normalized input-capacitor rms current vs duty cycle for 3-phase converter 00.4 1.0 0.2 0.6 0.8 input-capacitor current (i rms / i o ) 0.3 0.1 0 0.2 i l,pp = 0 i l,pp = 0.25 i o i l,pp = 0.5 i o i l,pp = 0.75 i o input-capacitor current (i rms / i o ) figure 18. normalized input-capacitor rms current vs duty cycle for 4-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v in / v o ) 0.3 0.1 0 0.2 i l,pp = 0 i l,pp = 0.25 i o i l,pp = 0.5 i o i l,pp = 0.75 i o figure 19. normalized input-capacitor rms current vs duty cycle for single-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v in / v o ) input-capacitor current (i rms / i o ) 0.6 0.2 0 0.4 i l,pp = 0 i l,pp = 0.5 i o i l,pp = 0.75 i o ISL6561
25 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com layout considerations the following layout strategies are intended to minimize the impact of board parasitic impedances on converter performance and to optimize the heat-dissipating capabilities of the printed-circuit board. t hese sections highlight some important practices which shoul d not be overlooked during the layout process. component placement within the allotted implementation area, orient the switching components first. the switching components are the most critical because they carry lar ge amounts of energy and tend to generate high levels of noise. switching component placement should take into account power dissipation. align the output inductors and mosfets such that space between the components is mi nimized while creating the phase plane. place the intersil mosfet driver ic as close as possible to the mosfets they control to reduce the parasitic impedances due to tr ace length between critical driver input and output signals. if possible, duplicate the same placement of these components for each phase. next, place the input and out put capacitors. position one high-frequency ceramic input capacitor next to each upper mosfet drain. place the bulk input capacitors as close to the upper mosfet drains as dictated by the component size and dimensions. long distances between input capacitors and mosfet drains results in too much trace inductance and a reduction in capacitor performance. locate the output capacitors between the inductors and the load, while keeping them in close proximity to the microprocessor socket. the ISL6561 can be placed off to one side or centered relative to the individual phase switching components. routing of sense lines and pwm signals will guide final placement. critical small signal components to place close to the controller include the isen resistors, r t resistor, feedback resistor, and compensation components. bypass capacitors for the ISL6561 and hip660x driver bias supplies must be placed next to their respective pins. trace parasitic impedances will reduce their effectiveness. plane allocation and routing dedicate one solid layer, usually a middle layer, for a ground plane. make all critical comp onent ground connections with vias to this plane. dedicate one additional layer for power planes; breaking the plane up into smaller islands of common voltage. use the remaining layers for signal wiring. route phase planes of copper fi lled polygons on the top and bottom once the switching component placement is set. size the trace width between the driver gate pins and the mosfet gates to carry 1a of current. when routing components in the switching path, use short wide traces to reduce the associated parasitic impedances. ISL6561
26 ISL6561 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) index d1/2 d1 d/2 d e1/2 e/2 e a 2x 0.15 b c 0.10 b a mc a n seating plane n 6 3 2 2 3 e 1 1 0.08 for odd terminal/side for even terminal/side c c section "c-c" nx b a1 c 2x c 0.15 0.15 2x b 0 ref. (nd-1)xe (ne-1)xe ref. 5 a1 4x p a c c 4x p b 2x a c 0.15 a2 a3 d2 d2 e2 e2/2 terminal tip side view top view 7 bottom view 7 5 c l c l e e e1 2 nx k nx b 8 nx l 8 8 9 area 9 4x 0.10 c / / 9 (datum b) (datum a) area index 6 area n 9 corner option 4x l1 l 10 l1 l 10 l40.6x6 40 lead quad flat no-lead plastic package (compliant to jedec mo-220vjjd-2 issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.18 0.23 0.30 5, 8 d 6.00 bsc - d1 5.75 bsc 9 d2 3.95 4.10 4.25 7, 8 e 6.00 bsc - e1 5.75 bsc 9 e2 3.95 4.10 4.25 7, 8 e 0.50 bsc - k0.25 - - - l 0.30 0.40 0.50 8 l1 - - 0.15 10 n402 nd 10 3 ne 10 3 p- -0.609 --129 rev. 1 10/02 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.

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